This invention relates to an address indication circuit for use in accessing a random access memory of a data processing system which carries out conversion between an original data arrangement and a modified data arrangement each of which has a plurality of data words arranged in channels.
As such conversion of the type described, interleaving processing is known wherein an original data arrangement is converted into a modified data arrangement which may be called an interleaved data arrangement. As will later be described with reference to a few figures of the accompanying drawing, the interleaved data arrangement is produced by giving the original data arrangement delays predetermined for each channel of the original data arrangement.
As will also later be described with reference to the other figures of the accompanying drawing, a data processing system disclosed in Japanese Unexamined Patent Publication No. Syo 55-70918, namely, 70918/1980 carries out conversion between the original and the interleaved data arrangements by the use of a random access memory (RAM). In order to provide the delays necessary for the conversion in the data processing system, the random access memory should be accessed by a specific address indication circuit. With this system, the random access memory may have a comparatively small capacity. However, the specific address indication circuit becomes intricate more and more in structure with an increase of the channels. In addition, the specific address indication circuit can not flexibly cope with a change of the delays for the respective channels.